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I've heard talk about how F4-based flight controllers can't natively support the SBUS receiver protocol without special circuitry. What does this mean and what hardware is needed to invert an inverted protocol like SBUS?

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A serial signal is composed of a series of High and Low electrical signals sent down a wire. In the standard serial protocol, a high signal is 0 and low is 1. In an inverted signal this is reversed so that a high is 1 and low is 0. You might think it makes more sense that low should always be 0 and high be 1 but electronics engineers decided that standard serial protocol should be the former.

To convert a standard serial signal to an inverted signal you run it through an inverter chip (which can be as simple as a single transistor) which will simply change all high signals to low and vice versa.

F3 and F7 chips have inbuilt inverters on their hardware uarts, which enable them to transmit or receive serial signals in any polarity. For some reason, F4's were designed without that feature and thus do not support inverted signals on their uarts.

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  • $\begingroup$ The reason F4s do not have it, but F3 and F7 microcontrollers do have it is because F3 and F7 chips are newer. $\endgroup$ – Luca Scheuer Apr 15 at 4:01
  • $\begingroup$ The STM32 F4 variant launched 2011, F3 in 2012. So the number is a name and not a version number that is incremented with each release. You can find the complete list on wikipedia: en.wikipedia.org/wiki/STM32#STM32_F3 $\endgroup$ – bingo-fuel Apr 16 at 13:27
  • $\begingroup$ To be clear, UART / Serial uses NRZ encoding, where as SBUS uses NRZ-I? $\endgroup$ – tuskiomi Apr 18 at 3:41
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In digital electronics, a signal is sent as a series of ones and zeros. In simple serial implementations, these are represented by zero volts and another voltage, typically 3.3V or 5V depending on the voltage of the system. Some systems use the higher voltage as the one and zero volts as the zero, but some are the other way around - hence, 'inverted', and a converter is required for interoperability.

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